Very often in late design stages of an integrated circuit, small timing and crosstalk violations are fixed manually as no tools currently exist to implement the fixes. The violations are commonly caused by constraint changes and functional changes before and during place-and-route operations. To keep the performance results of the integrated circuit consistent through the place-and-route operations, and the rest of the design development, manual interactions are often limited to only the violated parts. To find the best place to implement changes during the place-and-route operation, having all related information available in a bundled form is desirable. The related information includes areas of highest and lowest resistance of a net, highest and lowest capacitance to adjacent nets and the availability of faster, slower and different driver strength cell types for the current cells within the design. In addition, an automatic ability to write out engineering change order (ECO) files, when needed, or implement fixes on the circuit networks, where possible, during the place-and-route operations is also desirable.
Current approaches to implementing the fixes involve manual interactions of the engineers. The engineers have to find a correct solution by reading documentation and datasheets about the cells. A considerable amount of experience with the place-and-route operations is often helpful. However, the manual interactions consume significant time reading the large reports and are prone to human errors. Furthermore, a large number of different software tool licenses must be obtained to acquire the various tools used to analyze different aspects of the circuit design.